1. Field of the Invention
The present invention relates to a computer system and more specifically to the hardware time-out mechanism of a computer system.
2. Art Background
In a computer system, time-outs are used to ensure a temporal boundary of events. If two events (an initiating event and a terminating event) are not detected within a certain time period, a time-out has occurred. For example, in a computer system with a processor connected to several Input/Output ("I/O") cards, a processor reading an address location in one of the I/O cards will issue a read request to its desired I/O card. When a reply packet is received within a certain number of cycles after issuing the read request, no time-out is generated. However, if the read reply never comes back, the processor should not have to wait forever because the I/O card may not even exist or be in operation. Therefore, a time-out can serve to notify the operating system or the processor that this I/O card does not exist and the operating system should take whatever appropriate actions it is designed to do, for example, re-boot or retry. As shown in FIG. 1, time-outs are typically implemented with a counter 100 that is started and incremented at an initiating event 101. The counter 100 can then be disabled if a terminating event 102 occurs. If the counter 100 reaches a predetermined value 103 and a terminating event 102 has not occurred, then a time-out has occurred in the system. For example, an initiating event 101 in this system can be a processor executing a read to an address and setting a time-out value 103 which terminates or stops the counter 100 when the value is reached by the counter 100. A terminating event 102 such as an I/O device responding to the processor read with data will reset the counter 100 and no time-out has occurred. Typically, a valid bit 110 is set when an initiating event 101 is generated to start the counter 100. If a terminating event 102 occurs, the valid bit 110 is reset while the contents of the counter is disregarded. When the next initiating event 101 occurs, the valid bit 110 is again set and the counter 100 started. But, if the counter 100 is greater than the time-out value 103 while the valid bit 110 is set, then a time-out has occurred because the terminating event 102 has not been received.
For a typical computer system, it is desirable and necessary to detect multiple time-outs of events that start at different times. FIG. 2 illustrates a block diagram of components for detecting multiple time-outs. This typically requires multiple counters 200-203, although sometimes with a common prescaler 210 to set the period. Each counter implements a time-out for a different pair of initiating and terminating events. After each preset interval, the prescaler 210 will generate a pulse 211-214 to a corresponding counter. If the counter has reached a predetermined number when the pulse is received and a corresponding valid bit 220-223 is set for that particular initiating event, a time-out has occurred. As can be appreciated by those skilled in the art, implementing and detecting multiple time-outs would typically require duplicating the counters 200-203 and the valid bits 220-223 for each additional pair of the time-outs. Thus, if there were 16 time-outs it will be 16*2=32 flip-flops, plus the additional control logic. Given the fact that counters are typically quite large in terms of silicone area, replicating the counter circuit becomes a highly undesirable solution in a typical computer system.
Additionally, a computer system quite often has classes of time-outs and for each class of time-outs it is required to implement a multiple time-out mechanism, while the practicality of a computer system only needs one outstanding time-out event to generate further actions without regard to when the additional time-outs occur in each class. As such, within each class, the computer need not distinguish one time-out from another. For example, in a processor capable of issuing multiple commands to multiple I/O devices, all the processor needs to know is which I/O device experiences a time-out without regard to which exact address within the I/O device times-out before the processor re-boots or retries. With this understanding the need to replicate a counter and valid bit for each time-out pair becomes more undesirable and impractical as the number of devices increases linearly with the number of events in a computer system.